An electronic camera generally converts an optical image into a set of electronic signals. The electronic signals may represent intensities of light received by the camera. The electronic camera typically includes an array of image sensors which detect the intensity of light received by the camera. The image sensors typically generate electronic signals that have amplitudes that are proportionate to the intensity of the light received by the sensors. The electronic signals can be sampled and digitized to allow image processing.
Integration of the image sensors with signal processing modules is important because integration enables miniaturization and enhancement of imaging systems. Integration of image sensors along with analog and digital signal processing modules allows electronic camera systems to be compact, low cost and dissipate low amounts of power. However, the degree of integration is dependent upon the miniaturization of the image sensors.
Historically, image sensors have predominantly been charged coupled devices (CCDs). CCDs are relatively small and can provide a high-fill factor. However, CCDs are very difficult to integrate with digital and analog signal processing modules. Further, CCDs dissipate large amounts of power and can suffer from image smearing problems.
An alternative to CCD sensors are active pixel sensors. Several types of prior art active pixel sensor structures presently exist. However, each of the prior art active pixel sensor structures include features which limit the desirability of the specific sensor structure.
FIG. 1 shows a prior art active pixel sensor structure which requires four transistors Q1, Q2, Q3, Q4, a floating diode FD and a MOS capacitor CM1. Due to the large number of circuit elements, this active pixel structure requires a significant amount of integrated circuit area. The RST line of this structure allows the floating diode FD to be discharged. A PG connection includes a polysilicon wire. By adjusting the voltage potential of the PG connection, the MOS capacitor CM1 is created due to depletion of a channel region created under the PG connection. A TX connection is driven to a fixed voltage potential to provide a potential barrier for the MOS capacitor CM1. The depletion region which creates the MOS capacitor CM1 is generated by biasing the PG connection to a high voltage potential (Vdd). The MOS capacitor CM1 will accumulate electrons when exposed to light which excites the electrons. After a period of integration, the electrons accumulated on the MOS capacitor are transferred to the floating diode FD because the MOS capacitor CM1 ceases to exist. A signal voltage is stored across the floating diode FD which is proportional to the intensity of light received by the active pixel sensor. The SEL connection allows the signal voltage across the floating diode to be sampled. As was previously mentioned, the substantial number of electrical components associated with this active pixel sensor require a large amount of integrated circuit area which limits the fill factor of the sensor.
FIG. 2 shows a prior art active pixel sensor structure which requires three transistors Q5, Q6, Q7 and a photo-diode PD1. The photo-diode PD1 collects charge at a rate which is proportional to the intensity of light received by the photo-diode PD1. Capacitance coupled to the node FD accumulates charge as the photo-diode PD1 collects electrons. The active pixel sensor structure shown in FIG. 2 includes fewer transistors than the active pixel sensor structure shown in FIG. 1. Therefore, the active pixel sensor structure shown in FIG. 2 is smaller than the active pixel sensor structure shown in FIG. 1. However, miniaturization of an array of these pixel sensors is limited by the fill factor of the pixel sensors. To improve the fill factor, the number of transistors in each pixel sensor must be further reduced.
FIG. 3 shows a prior art single NPN bipolar transistor active pixel sensor. The size benefits of including only a single transistor within the active pixel sensor are negated by the size requirements for implementing the active pixel sensor. That is, the single transistor is an NPN bipolar transistor which requires an N-well when the active pixel sensor is implemented using a P-doped substrate. Typically, a N-wells are large when implemented using a CMOS fabrication process. Furthermnore, a base node of the NPN bipolar transistor is essentially floating. Therefore, resetting the active pixel sensor at the base node is not very easy. As a result, this active pixel sensor can suffer image lagging.
FIG. 4 shows a prior art passive pixel sensor structure which requires two transistors Q9, Q10 and a photo-diode PD2. The photo-diode PD2 includes a junction capacitance CD. An output of the passive pixel is connected to a bitline which includes a bus capacitance CBUS. The transistor Q10 is turned on when selecting the active pixel sensor. The capacitance of the junction capacitance CD is effectively connected in parallel with a capacitance of a bus CBUS. The fill factor of this pixel sensor is high. However, the signal to noise ratio is not scalable with an increase in the number of pixel sensors within an array of the pixel sensors. A voltage potential created by charge stored on the capacitance of the photo-diode is shared with the capacitance of bus. When the active pixel sensor is selected, the voltage charge collected on the capacitance of the photo-diode is greatly reduced as the charge on the capacitance of the photo-diode is shared with the capacitance of bus. The capacitance of the bus increases as the size of the active pixel sensor array increases. Therefore, the signal to noise ratio of a signal generated by the active pixel sensor is greatly reduced when the active pixel sensor is within a large array of active pixel sensors.
It is desirable to have an active pixel sensor which is physically small and provides a high fill factor. The active pixel sensor would provide low-noise read-out signals, electronic shuttering and anti-blooming. Further, the active pixel sensor could be integrated with image processing circuitry and fabricated using a low-cost CMOS process.